1. Field of the Invention
This invention related to integrated circuits, and more particularly, to the testing of integrated circuits having I/O pins that support for plesiochronous interconnects.
2. Description of the Related Art
Plesiochronous signaling is a form of high-speed signaling capable of enabling chip-to-chip communications having transfer rates of up to 10 Gbits/s over a single interconnection. As such, plesiochronous links are capable of significantly higher data transfer speeds than traditional synchronous links (synchronized to a global clock) or source synchronous links (synchronized by a clock transmitted concurrently with the data). Instead of relying on a separate clock signal, plesiochronous links utilize an embedded clock signal, which is recovered from transmitted data by a clock-and-data recovery (CDR) circuit.
Due to the obvious speed advantages of plesiochronous links, many systems now utilize integrated circuits (IC's) configured to communicate with each other in this manner. However, configuring the I/O pins of an integrated circuit package for plesiochronous communications may present a significant obstacle to performing manufacturing tests thereupon.
Manufacturing tests of integrated circuits on automated test equipment (ATE) requires the ATE to be able to compare chip responses on output pins repeatedly on a per clock cycle basis. These chip responses are generated by logic internal to the integrated circuit (i.e. core logic). Comparisons of expected responses by the core logic to the actual responses require the use of a reference clock in the ATE. However, transmitter circuitry configured for plesiochronous transmission of signals does not satisfy this requirement since plesiochronous signaling does not rely on a clock. Furthermore, since ATE does not have the capability of recovering a clock from the data stream, a typical ATE system cannot interpret data received from a plesiochronous transmitter pin.
To work around this limitation, IC's configured to transmit data plesiochronously may include dedicated test pins that can synchronously transfer responses to ATE. However, this solution is expensive, as it consumes silicon area on the die and pin count on the IC package. Furthermore, the number of dedicated test pins may be limited by other specifications of the IC. Limiting the number of dedicated test pins may in turn reduce the communications bandwidth between the IC and the ATE, increase the amount of time necessary to test the IC, or cause a reduction in the amount of testing that can be performed. Thus, for IC's configured to transmit signals plesiochronously, testing may be significantly constrained.